Fpga altera jobs

We need support for TCL scripting, FPGA projects. Tcl sripts will be used to compile and simulate VHDL code, synthesize, P&R and analyze reports

I am looking for an experienced Verilog or VHDL engineer to help me explain and design Number theoretic transform (NTT) which is the most efficient method for multiplying two polynomials of high degree with integer coefficients, using FPGA. The project has specific requirements and I will provide detailed specifications. The desired implementation platform is Xilinx FPGA using Vivado and the deadline for the project is 1-2 weeks. Ideal skills and experience for the job include Verilog or VHDL programming, FPGA design, and NTT knowledge.

Looking for developing Software and Hardware for Power Electronics Controller using DSP (TMS320xxx), CLPD, FPGA and MCU's Based for power Control through thyristors and IGBT's

I am looking for an experienced FPGA developer to create a custom bitstream for my CVP13/BCU1525 FPGA project. must be an optimzed bitstream for both cvp13 fpga and bcu1525 fpga. must include software to operate the bitstream i have the desired format and specific program i want modified "it can be found on git hub. The desired outcome is improved performance, and I have specific software requirements for the project. Ideal skills and experience for this job include: - Expertise in FPGA development - Experience with CVP13/BCU1525 FPGA boards - Ability to customize bitstreams for improved performance - Ability to work with specific software requirements If you have a track record of successfully developing FPGA projects and can ...

We are seeking a VHDL FPGA programmer to develop a program for data encryption and decryption with a high level of security. The ideal candidate should have experience in VHDL programming, FPGA design, and encryption/decryption algorithms. Functionality: - The program should provide high-security data encryption/decryption that meets the client's requirements. Encryption/Decryption algorithms: - The client needs suggestions for encryption/decryption algorithms that meet their high-security requirements. The ideal candidate should have experience in suggesting and implementing secure encryption/decryption algorithms. Level of security: - The client requires a high level of security for the encryption/decryption process. The ideal candidate should have experience i...

I am looking for an experienced freelancer to work on an FPGA based project. The main goal of this project is performance optimization, and I am looking for someone with experience using the Xilinx platform, and coding in VHDL. I am looking for someone who can ensure that the project turns out as expected and meets all my requirements. Additionally, I would like the outcome of this project to have a positive impact on my organization's performance. The freelancer I choose must have in-depth and up-to-date knowledge of the FPGA architecture as well as memory control, interfaces, and system design. He/she should also possess excellent programming experience and be able to provide detailed reports and documentation in a timely manner. Moreover, I need assurance that this ...

I am looking for someone to develop a project that will allow data to be transmitted from my Field Programmable Gate Array (FPGA) to a PC. The connection type that should be used is USB and the language used to communicate must be Verilog. Data that needs to be transmitted is text only. I need a detailed solution that can handle transmission of data in a smooth, consistent manner. It should be able to identify events and their associated data while being reliable and efficient. The hardware and software involved should be thoroughly tested and debugged. The solution should also be documented and include any necessary reports/specifications. The project should be delivered in a timely fashion.

I am looking for a freelancer who can design and implement an LMS adaptive filter in the structural level modeling using an FPGA. The ideal candidate should have experience with Xilinx FPGA devices and be able to work with high-frequency signals (>10kHz). The desired level of accuracy for the filter design is medium (±1% error). Specifically, the project requirements include: - Design and implementation of an LMS adaptive filter in the structural level modeling using an FPGA - Working with high-frequency signals (>10kHz) - Experience with Xilinx FPGA devices - Achieving medium accuracy for the filter design (±1% error) If you have the necessary skills and experience, please submit your proposal.

I am looking for an experienced freelancer to help me with a project where I need to transmit data from a Xilinx FPGA to a PC through UART. The data size that needs to be transferred is 1-10KB. It is critical that the selected freelancer has prior experience in this specific area. I'm looking forward to working with you!

I would like a multi-class Zynq FPGA tutorial, at first with the most basic concepts (from zero) and increasing the level with each class, starting to beginners and finishing with a professional mastering of the subject, to learn and understand completely how to use Zynq and become proficient of the subject. The minimum total duration of the course with all classes must at least 8 hours. I need good quality on the recording and the edition of the course. Also, the content has to be original, to be able to use it without restrictions. We will sign a contract of copyrighting cession before ending the project.

I need help with transmitting data from FPGA board to PC using UART

I am looking for a freelancer who can help me speed up TFTP transfer in my Xilinx SP-605 FPGA board (Spartan 6). Currently, the transfer speed is about 1MB/s and I need it to be faster. Ideal skills and experience: - Experience with Xilinx SP-605 FPGA board (Spartan 6) - Experience with Xilinx Platform Studio, and Xilinx SDK (microblaze) - Strong understanding of TFTP transfer protocols - Knowledge of hardware constraints and optimization techniques - Experience with network interfaces and memory bandwidth Constraints: - Must consider hardware constraints - Must use Xilinx SP-605 FPGA board (Spartan 6) - Must consider software constraints - Use Xilinx Platform Studio (XPS) 14.1 - SDK - Microblaze I already have an existing XPS project, and Microblaze ...

We are looking for an experienced FPGA designer to create a design for the PCI Express protocol on the Xilinix Virtex-7. We're working on a project in which we have two Virtex-7 FPGA development boards, connecting them together directly through its on-board PCIe connectors using the AXI-PCIe IP core with MircoBlaze as processor designed in block diagram. In the design, one FPGA board programmed as a root complex, another board programmed to be an endpoint device. We're trying to make them communicate with each other; but, the root complex device isn't able to detect the end-point device and I don't have success to make them working. Ideal skills and experience for this job include: - Expertise in FPGA design and implementation - Strong und...

I need to control the buck converter using a current mode control in digital form. That means i need to use digital PI, ADC converter, Digital PWM. For these digutal controlling parts I have to write verilog codes or have to use IP's in vivado to implement on FPGA. At the end I need to do PCB design for the buck converter and after that I have to combine them and observe the results on oscilloscope.

...will provide experience of the problems and decisions in developing co-design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem. HW/SW Specs: The target embedded systems platform can be either the AlteraDE0 FPGA platform or the PSOC. Both devices/boards provide the opportunity to implement low-level, interrupt driven, device drivers along with the custom hardware. Altera DE0 Board: This board has a Cyclone III FPGA fitted. This supports a ’soft-core’ processor integrated with custom hardware. Using the Nios2 softcore CPU as a base you will implement a system to control a robot arm. There is the potential to use a small embedded O/S, FreeRTOS, uCLinux, or to wr...

Looking for someone that is an expert in digital data acquisition and data processing. I have a transmitter that has a bandwidth of 10mhz that am hoping to have a reciever that can handle this signal. The ADC should be able to handle 4 to 6ghz and 1 to 20mhz bandwidth. I want a custom External ADC with FPGA. I do not want to use modules. I want someone that has built a generic PCB for this that has a high success rate

Hello! I am in need of a freelancer to help me with a project creating a car elevator controller. The controller will be created using Vivad Verilog code and fpga implementation. I am looking for someone who can provide a detailed project proposal in their application. It is also important they have past work and experience in the same field. I won’t need any type of remote access for this project so please do not include any advice on that as part of your proposal. If you believe you are suited for this project and would be interested in working with me, please apply and include your detailed project proposal. I look forward to hearing from you!

I'm looking to hire an experienced Xilinx FPGA programmer to help with a project. Located near Mumbai suburb. The ideal candidate should have extensive knowledge in FPGA programming and specifically working with Xilinx FPGAs. Please provide some proof of your skills and experience with coding for FPGAs. I look forward to hearing from you soon!

...practical demonstration will take place last week. Using BUT e-learning, students submit a link to the GitHub repository, which contains the project in Vivado, the necessary images, documents and a descriptive README file. The submission deadline is the day before the demonstration. The FPGA source codes must be written in VHDL and implementable on the Nexys A7-50T board in the development tools used in the laboratory during the semester. Make testbenches for all your new components. Physical implementation on FPGA is necessary, computer simulation is not sufficient. Never, ever use rising_edge or falling_edge to test edges of non-clock signals under any circumstances! In a synchronous process, the first thing to do is test the clock edge, then synchronous reset. The...

BCD multiplier development using Verilog HDL for Xilinx FPGA technology Input/Output Format: - Desired input/output format is Binary Testbench: - Testbench required for the Verilog code Ideal Skills and Experience: - Proficiency in Verilog HDL - Experience in BCD multiplier development - Expertise in Xilinx FPGA technology - Familiarity with Binary input/output format - Ability to create a testbench for Verilog code Goals: - Develop a functional BCD multiplier using Verilog HDL - Ensure the Verilog code passes the testbench - Optimize the design for Xilinx FPGA technology.

We want a software developer for CIJ Printer using Xilinx FPGA and stm32f429 as a processor.

using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C

I need a full verliog code that will output a "32-bit microprocessor using an FPGA board" 1. High level text description to describe HOW you are implementing your project. 2. DETAILED Block Diagram(s) showing design and detailed interconnections. 3. List of tasks completed 4. List of things I need to simulate, debug, and demonstrate 5. Data sheets for each IC used in your design. 6. Worst Case analysis - show tables / spread sheets in progress in process for Noise margin, Loading, Timing 7. I WILL NEED A VIDEO EXPLAINING HOW THE CODE WORKS (IN ENGLISH) 8. ALSO PICTURES OF THE CODE RUNNING SMOOTHLY NO PLAGIARISM PLEASE PLEASE COME UP WITH YOUR OWN CODE

FPGA to control and monitor a motor for avionc application, DO-254 DAL-B. the motor uses an ARINC 429 to communicate with external devices

The main task would be initiating ways to create an ethernet communication through xilinx software for zcu216 board. ex:- PS and PL based ethernet communication, use of LWIP etc etc. We need to check the communication of signals to and from fpga board. At the end we have to create a loopback , to acquire and generate signals in a loop method. Further info in detail will be provided to review the task.

I'm looking for a highly experienced Python expert with significant experience working with FPGA to help me with a project. I will share the work details in chat. My budget for this task is maximum 50 usd so don't overbid I am expecting to engage the successful candidate for a minimum of 4-6 months, and I am open to a longer project duration depending on my project requirements.

Need to localize indoor position for multiple people using uwb tag and also need to use fpga

...and drop down menus · Hands-on experience on various microcontrollers AVR/PIC/ARM/STM32F4/Xilinx XC7Z020 · IDE experiences on AVR Studio/ MPLAB/Keil IDE · Peripherals like - UART/SPI/I2C/ADC/PWM FPGA interfacing includes C Code for: ADC IC with SPI interface. DAC IC with SPI interface. 12 Bit Parallel Data interface with DAC IC. 8 Bit Parallel Data interface with DAC IC for sine wave generation. 10 PWM channel interface. SDRAM interface. SD Card Interface. USB interface RS232 Interface Current Steering DAC interface interaction experience on FPGA Able to prepare and implement the Pre-production plans like Bill of material preparation, Assembly instructions and final quality testing procedures. ...

Embedded Linux with FPGA capability. From VHDL to application level programming.

We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language

I am searching for an individual who possesses strong expertise in FPGA and Zynq AX7020 IC, specifically to assist me in installing OpenWiFi on my FPGA. All necessary information and resources are available on Github. The ideal candidate should be highly experienced in installing OpenWiFi and familiar with both FPGA and Zynq AX7020 IC. They should be able to provide clear guidance and instructions on the installation process. This project is critical to me, and I need someone reliable and highly skilled who can deliver quality results. If you have the necessary expertise and skills to help me with this project, please get in touch. I'm looking forward to hearing from you.

Looking for FPGA Developer who has experience in VHDL on SoC FPGA architecture

I’m looking for a talented freelancer to help me design a LIN Bus controller FPGA, in VHDL. To be considered for the job, candidates should include past work in their application and provide relevant experience related to this project. Any working code previously developed is a plus. Deadline for the delivery 20th April 2023. A quotation is required, together with the proof of previous expertise of the working code already developed It will be required to 1. deliver VHDL source code for LIN master bus controller 2. testbench with a Verification module, or any other sort of mechanism to emulate a node 3. Integration and testing of a simple test code on hardware provided by us 4. documentation

Europe, Italy timezone preferred. Lead the activity for porting FPGA design to Silicon technology (memory replacement, ...) Carry on simulations of the updated RTL design to check that the functionality remains unchanged Execute static and formal verification of RTL code using appropriate tools Run trial synthesis on the RTL design and check the timing violations Lead the activities for SoC sub-block Static Timing Analysis. Required Skills (expert): VHDL language Digital ASIC design flow Use of digital simulations with standard industry simulators (Mentor QuestaCore) Static and formal RTL verification (e.g. Synopsys Spyglass) Synthesis tools (e.g. Cadence Genus) UVM and System Verilog test benches

Hello! I got a task at college to use the FPGA Spartan 3E board for image processing. The image data is written into the FPGA, and then the image is processed by adding an effect, such as blur, darken, or something similar. The user selects a specific switch to choose which effect to apply. The processed image data is returned to the computer, and this data can be converted to BMP format to see the final result. It would be desirable to use the UART protocol. I am willing to pay $120 for this project. If you are interested, please let me know and we can discuss the details. Thank you :)

Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?

design beamforming antenna using standard algorithms in x86, FPGA. RF engineering and radar, 5G Output will be working algorithm and prototype of beamforming in 5ghz - 12ghz x-band range

... 1) CNN to predict Blood pressure from PPG on Nexys A7 FPGA. 2) input to FPGA should be analog PPG signal. 3) output should be SBP and DBP values which has to be displayed on LCDof ARTIX-7. 4) Training and testing of CNN should be done using python. 5) A report describing the system and it's operation with all the codes. Certain Points for More Clarification: 1) the CNN should be "1-D CNN" and the database should be kaggle database. 2) python file for training and predicting BP values. 3) vivado hlx for CNN with weights from the above mentioned python training. 4) simulation from vivado for CNN and printing BP values with accuracy greater than 95%. 5) implement CNN thus created on Nexys A7 100T FPGA board with "...

I want someone to design using FPGA and Microcontroller

I am looking for an experienced Altium PCB design who has worked on complex PCB design using Altium 365. - Zynq ultrasclae+ MPSoc FPGA - AD9361 - AD9371 I only need individual freelancer. Full-time available can work on US time zone should reply ASAP. Please share your portfolios what you have done in similar fields.

...configure the radix of outputs as “binary”. 3) Create an XDC file to map your circuit IOs to the Basys3 board. Use slide switches for the 4-bit input data operands, carry in, and functionality mode selection bits (S2-S0). Use LEDs to display the outputs: result and carry out. 4) Synthesize and implement your design in Vivado, then generate bit stream & program the FPGA board. 5) Test and verify the operation of your design on the FPGA board for all arithmetic & logical operations using a subset of input data patterns you choose from the functional table....

We are looking for a FPGA programmer who can debug the code for FPGA circuit and code the FPGA accordingly. I have few details that all I have. Please review the files attached before placing the bids.

Need somebody who has done procesing of signals in realtime with some DSP chip that is fast enough, and within normal consumer budget. Or FPGA, or whatever hardware configurations, that are available. The attached spike has a duration of aprox 7 microseconds and an amplitude of 0.1 to 5.5 V. The input of the spike is around 200hz. We are trying to push it to 500hz or more. I need sampling on each channel at least 7msps. The proccesing each sample set and curve fitting, to get the peak perfect precision mathematical peak with a precision of 2 miliVolts. Then the data is interpreted in order to maintain the Curve, and not get saturated, (with that triangle-ish shape img6303) and a control signal is emitted to lower the excitation and come back to the curve normal shape. These...

I have a board i need to fix for an equipment in my store. Looking for an FPGA expert that can debug the program files i got from the manufacturer. I was told this should be simple for someone that knows what they are doing.

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Devlop a model to detect skin cancer using conditional GAN translation and apply on cnn models. Execute the model on fpga processor

I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

QPSK modulation and demodulation with Turbo Encoder/Decoder, Interlever, Channel Estimator, Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design d...Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design development) on Zynq 7035 and 7030. Linux Based OS to make Linux OS executable files. Hardware: Zynq 7030 and 7035 FPGA and AD9361 Tr...

To interface lattice FPGA with ultrasonic sensor (5 )and lidar sensor(4) with the provision for connecting an MIPI based camera module (no AI stuffs),the FPGA would be connected to stm32h7 via SPI interface . More details via chat including the sensor type

...local server time, current BTC network difficulty, The Block number that the pool is currently working on, Report on how far past 10 minutes the last block found on the network, Server "Luck", blocks found by the pool in the past, Records of the payouts on each block found. 18. Identify the type of "chip" that is connecting to the pool so that stats can be made on which types of miners (CPU,GPU,FPGA or ASIC) are working on the pool with the option to show which type of chip has solved x number of blocks. 19. Pool stats should be dynamic so that they show miners their potential payout page to give active miners an idea of what their payout would be if a block was to be found at that time. 20. Pool source code built will be exclusively used for this project and ...