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    2,891 fpga jobs found, pricing in INR

    Assalam o alaikum !!! I am looking for fresh electrical engineers with specializations in all domains of electrical engineering including: 1) Electrical Power 2) Electronics 3) Telecommunication 4) Computer architecture 5) Embedded systems I am looking for experts in following domains: • VHDL/Verilog, LabVIEW/Multisim/PSPICE • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • Matlab/SIMULINK, Network Simulator NS2/NS3 • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications.

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    An expert with FPGA is needed. The expert must be proficient with Quartus Prime.

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    I have a Xilinx FPGA project and I would like to update it to use a newer Xilinx FPGA. The project can be found here: I need to convert this HDL from a Spartan 3A device to a Spartan 6 device: This project utilizes a ZPU GCC compiler to synthesize the project which is unique for some Xilinx FPGAs.

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    I'm going to build the miner with FPGAs, not using ASIC. Please submit proposal only with experience in designing similar things.

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    I need a Microelectronics and VLSI Expert who knows about FPGA and VLSI like things and have good knowledge in Analog and Digital domains as well.

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    We are using Xillinx fpga developing a lidar control system, involving an AMS-gpx2 TDC chip and a dual axis scanner which need two independent sine wave (DAC+class AB audio amp), and a gyro at some point. We have system build but need to be professionally improved, I’ll need a GUI to change the two sinewave frequency (180 to 420Hz) and maybe amplitude too, starting pulse duration (5 to 30 no) for tuning

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    I need a developer who can build a miner for sha256d algo (including bitstream) for u200 fpga’s FPGA’s are located in aws data center, We could give you a ssh or rdp connection to them.

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    Featured Urgent
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    I am looking for a fpga developer for a crypto mining project. More details will come soon

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    We have a client project in Node.JS and C++ Do you have experience with Raspberry Pi and Booting Kernels? Please respond with your experience. Have you worked with FPGA?

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    Hi, I wou...PCB includes ZYNQ FPGA, and some interfaces including PCI-E, ethernet, FMC LPC, USB. The schematics are designed based on the development kit so most of the work is copied from the development kit. Responsibilities: I am looking for a person who has deep knowledge of the above-mentioned interfaces and has designed similar systems before. Since most of the schematics are already designed in Altium, I need a person who can verify the design and suggest the required changes. Part 2: I would like the person to get the board manufacture in China (I will provide my manufacturer and take care of cost) and then bring up the board, load the software and test the interfaces if they are working well. All the software is available and there is no need to write any software for <...

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    Hi, I have one FPGA Xilinx Alveo U250 Deployment VM - Ubuntu18.04 I can't get it to work with any of the cryptocurrency mining software, as those apps don't see/recognize the card at the moment. I am 100% sure that this can work, just need to figure out how specifically or what else needs to be done here. I am not sure what I still need here, what driver or tweak is required, or whether we need to even write a custom code for the two to work together. Please contact me only if you know exactly what this is all about and in your application for the job, do your best to get my attention by mentioning how you plan to fix this for me. Plain applications with bunch of qualifications and past experience doesn't do much for me. Mentioning that you read my post here and...

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    hi i want to create one image processing code for attached images . final image has different. This small dot can be any where in this white line . can you do this? code should have to find this dot in blue red ,yellow etc apart from can use only Verilog or VHDL here please send your price for this and time . Then we can start.

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    Create a software that reads/writes memory to a process located on target machine through DMA. PCILeech is best resource to learn/use. Experience with DMA devices is recommended Please contact me, flexible on price

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    My project is the implementation of machine learning by using FPGA. We will have already trained network and we will improve the deep neural network like speed up and accuracy or increasing throughput. By using some techniques, Now I get to the practical side. And MAC operation (multiplication between weights and input features and then adding to bias) start we multiply 32-bit floating-point and then use the register to store the result of MAC.

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    We are looking for a very experienced developer to do this FPGA task inside the document file for us !!!! The maximum budget is: 70 AUD timeline : 3 days and should show daily process! our terms: we will not create milestone until we see any progress as we already heard 100 times yes we can do it and it was just a waste of time and money. if you are interested let us know Note: we have many projects that need to be done so the one who will do this perfectly will have more and more work during this month Also, we are offering a good bonus if you cooperate with us in the way we want please check the attached document file for all the information you might need

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    Goal is to develop the FPGA (Lattice, Xilinx, ...) based camera converter from MIPI CSI-2 to JPEG over SPI. We need the working prototype arounf end of february (2022) Deadline of the final version is the end of March. Project result must be the production ready PCB design. Key specifications are: 1. STM32 is connected to the FPGA: it receives the JPEG frames over SPI and controls the camera via I2C. FPGA triggers GPIO when new frame is completed. STM32 can do modifications on the camera settings and video stream. Additional tasks of the FPGA are the init-reinit of internal buffers, modules and stop video stream receiving cycle when MCU sends stop signal (using GPIO). In summary, FPGA must handle the situation when no input from the camera and the ima...

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    Hi. Do you have heavy experiments on Lattice FPGA design and IP programming? As I wrote in the title, the goal is to reproduce the MIPI CSI-2 to DVP (DCMI) conversion of the camera.

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    Hi. Do you have heavy experiments on Lattice FPGA design and IP programming? As I wrote in the title, the goal is to reproduce the MIPI CSI-2 to DVP (DCMI) conversion of the camera.

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    Hi. Do you have heavy experiments on Lattice FPGA design and IP programming? As I wrote in the title, the goal is to reproduce the MIPI CSI-2 to DVP (DCMI) conversion of the camera.

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    Hi. Do you have heavy experiments on Lattice FPGA design and IP programming? As I wrote in the title, the goal is to reproduce the MIPI CSI-2 to DVP (DCMI) conversion of the camera.

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    Control DC motor by pulse frequency modulation (PFM) IN VHDL . I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite) End of the project I need a report

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    Hi Yashwant D., I noticed your profile and would like to tutor me in HW/SW co-design for FPGA based acceleration.

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    Bid only if you an expert in Finite Element Method and you can also work on python at the same time. I have a task that involved FEM and python at the same time. I will share full details to the selected freelancer.

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    I want program code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite) and I hope all of these including in the report also simulation in one report

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    I am looking for a real-time A-law/U-law encoder written in VHDL for implementing in a Lattice XP2 FPGA. The input to the encoder will be 16 bit PCM16, the output will be 8 bit a-law/U-law. The PCM16input will comprise of 24 channels. The CODEC will have 1 16 bit input. The 2k channels will be fed into the codec sequentially in blocks of 32 16bit samples. The CODEC shall handle a total of 10 Megasamples/second in real time. Each block of 32 16bit PCM data will be accompanied with a 4 bit channel number 0-23. The 8 bit companded output should have an extra 4 bit output that will hold the channel address that corresponds to the PCM channels from which it was created. The target FGA is a Lattice XP2-8 but the code will be demonstrated in the Lattice XP5 eval board as attached.

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    Port design from Max10 FPGA to Xilinx Zynq

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    NDA
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    Hello, I need design video transivver use de2-115 FPGA use SystemVerilog, ethernet and usb camera Rettru Mini HD 1080P. Video must be encrypted aes-256. De2-115 need recive command over ethernet for start/stop with host verification.

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    This project requires an Experienced Embedded Programmer. Prior experience in writing Interrupt Service Routines in Linux running on FPGA cards, YOCTO, as well as PCIe Interface is needed. Familiarity with RISC-V architecture is a plus.

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    I would like a FPGA miner for Equihash 125,4

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    Hi Looking for person who can support work from office or concern that can contract people to work for projects ( test bench development/ requirements writing / development and implementation tests/ simulation/ function coverage ) UVM / SYSTEM VERILOG must.

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    Assalam o alaikum !!! I am hiring electrical engineers for working on my projects in following areas of electrical & electronics engineering: 1) FPGA (VHDL/Verilog) 2) Matlab 3) Multisim I have a lot of work in all the fields mentioned above. Its a big opportunity to work with us for long term basis. Even if you are a new freelancer, feel free to place your bid. I AM HIRING EXPERTS FROM PAKISTAN ONLY

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    To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short period of time. If you think this fits your skills, let me know and lets discuss things further!

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    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit (DE10-Lite) and I need report about a project

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    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

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    1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. Optical Data link 5 Networking concepts

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    Write a program using QUARTUS ALTERA to work on De1-SoC FPGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be designed must provide control of the brightness of a single or multiple LED ‘s using values from an Absolute Contacting Encoder (128 positions). In addition, the circuit must display a decimal value of the LED intensity (0-127) by using three seven-segment displays. The circuit contains four logic blocks and 3 external components (Figure 1). The logic circuits are: • Code Conversion Table • Binary to BCD 3 digits (Decimal Values) • LED Brightening Control (PWM) • Seven Segments Decoder

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    Title of the project HDL Digital Signal Processor core for FPGA implementation Deadline is in 15 hours budget is 20$ requirement for the scope will be through the chat Thanks

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    I need someone to code me FPGA for financial markets

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    This job consists of implementing into a Xilinx Zynq three pipelines into vivado 2019.1: A phase lock loop using fixed point A frequency lock loop A delay lock loop Timeline: 3 weeks

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    Car parking system counting from 0 to 99 in 7 segment using vhdl , fpga I have the code and testbensh but I have a problem when I click on the push buttons the 7 segment does not show the numbers Model of fpga kit=> (( rz easyfpga a2.2 ))

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    Design Problem specification: To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such...considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the

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    Implement an FPGA-BASED ADAPTIVE NOISE CANCELLING SYSTEM according to the first paper and provide a full report of the works done. After that study available solutions for binaural rendering and extend the previous experimentation to other rendering solutions according to the second paper with a full report

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    looking for an expert in FPGA programming who can help me to interface an ADC to an FPGA using Vivado design Suite. The connection between the ADC and the FPGA is via FMC connector. The FPGA board that i am using is a Nexys Video board which mounts an Artix-7 FPGA. I need to understand how trancievers work and how to use transceivers in order to connect the Nexys Video and the ADC. The model of the ADC is probably the AD9689.

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    I developed a system that consists of 2 camera and 1 ethernet. The FPGA will get the image sensor data from 2 cameras and will process algorithm on the images. After processing, FPGA will send streaming data and processed data to the computer via Ethernet port. The protocol will be based on TCP/IP. I am looking for a long-term partner. I have many projects, so this will lead to other opportunities.

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    Recreate an FPGA simulation based on an open-source project programmed onto an MCU and communicate with the FPGA via SPI. Logic Analyzer captures would be provided for reference.

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    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

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    Hi Ahmed M., I would like to discuss with you my project. I need your mentorship and guidance from an experienced guy like you to have my project done by myself, is this possible? We can discuss more details over the chat. Thanks, Omar

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    i have Xilinx FPGA BCU/VCU1525 Card, i want to bit Stream for Ethereum Coin, and i have also vivado lab 2020,

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    Modify a existing controller on a FPGA (Cyclone III), which is used to calibrate the coefficients of a filter on another demo board. Already have a prototype, but needs to run modelsim and to modify existing verilog codes. Need someone who has a strong background with Quartus and FPGA design. Thank you.

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    ...separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board. The documentation should show justification for any design decisions that you make as well as development logs for both hardware and software. Evidence of approaches used for the codesign, co-implementation, co-testing, co-integration, and system integration must be provided. This assignment will provide experience of the problems and decisions in developing co-design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem. HW/SW Specs: The target embedded systems platform can be either the AlteraDE0 FPGA...

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