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    1,294 verilog projects jobs found, pricing in INR
    Verilog Servo controller 6 days left
    VERIFIED

    I'm looking for someone who can write me a verilog HDL code for a servo controller

    ₹2254 (Avg Bid)
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    1 bids

    The project details are in the files: [url removed, login to view] or [url removed, login to view] Same file different format.

    ₹1932 (Avg Bid)
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    5 bids

    create a digital design that can function as a four-bit full adder or a four-bit subtractor depending on state of switch(on or off)

    ₹1417 (Avg Bid)
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    7 bids

    need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works

    ₹1545 (Avg Bid)
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    11 bids

    We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers

    ₹14175 (Avg Bid)
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    5 bids

    I need a verilog code for recursive karatsuba multiplier for 16bit signed integers.

    ₹12538 (Avg Bid)
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    6 bids

    ...Proven experience in delivering at least one complex FPGA design project  VHDL, Verilog based RTL design and development  VHDL, Verilog based verification and validation  Familiarity with Xilinx ISE, Vivado Design Suite  Should have worked on ARM SoC based FPGA projects  High Speed Data Acquisition systems  Good knowledge on Timing constraints

    ₹141983 (Avg Bid)
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    5 bids

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you .

    ₹7083 (Avg Bid)
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    15 bids

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you . thanks

    ₹9723 (Avg Bid)
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    8 bids

    HI, till my project deadline is tomorrow I decided to send it one more time.(I mean who want to do this have to do this in one day). so if you think you can't do whole of the steps just post me that can complete which steps till tomorrow(cause I'll accept that too). project is in file below.

    ₹2125 (Avg Bid)
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    3 bids

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you .

    ₹3220 (Avg Bid)
    ₹3220 Avg Bid
    1 bids

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you . thanks

    ₹3220 (Avg Bid)
    ₹3220 Avg Bid
    1 bids

    HI, till my project deadline is tomorrow I decided to send it one more time.(I mean who want to do this have to do this in one day). so if you think you can't do whole of the steps just post me that can complete which steps till tomorrow(cause I'll accept that too). project is in file below.

    ₹2576 (Avg Bid)
    ₹2576 Avg Bid
    2 bids

    verilog expert needed to do a project on pipelining

    ₹990 / hr (Avg Bid)
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    23 bids

    design an Sdram ddr using verilog and test, verify it using Synopsis and TETRAMAX ATPG. finally verify the same design in FPGA.

    ₹21442 (Avg Bid)
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    4 bids

    looking for someone who can write a code to parse below code(using pyparsing) immediately : module module-name(input a, input b, input c, output r); wire mid1; mid1=a&(~b) wire mid2=b|c; wire mid3=a|c,mid4=b&c; wire mid5,mid6; mid5=a|(~c); mid6=a&b; r=mid5|mid6 endmodule *we have 4 ways to define wire as shown in above exampl...

    ₹6632 (Avg Bid)
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    7 bids

    I want someone who can help me to read the results data from FPGA board on MATLAB software. Verilog HDL language will be used.

    ₹4894 (Avg Bid)
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    14 bids

    need some help with verilog code.

    ₹1098 (Avg Bid)
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    21 bids

    Code for a specific signal passing through some noise being received on the other side. Complete with testbench

    ₹10252 (Avg Bid)
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    17 bids