The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact
...ability to extract and critically evaluate data for an unfamiliar digital design problem. • The application of appropriate design methods to the VHDL design. • The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors. • Ability to implement your design solution on a commercially available digital Computer
We want someone who can program a mobile game. We will of course pay via paypal or if you live in Sweden we can do it via the app ''Swish''. We will explain what the concept of the game is. Contact me on email for further details: [Removed by Freelancer.com Admin]
I need an android app that will have 1) a splash screen 2) a main screen that displays all available chapters 3) chapter display screen that shows one page at a time, with page turning animation 4) upgrade page that will allow paid users to access all chapters, (free users can access upto 5 chapters) 5) share button 6) update button to download files from server 7) in app payment for upgrade. The...
I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be
Design specific scheduling project for iPad. If you designed scheduling before - big plus. Show me what is done. Deliverables: Sketch files
3 to 5 wordpress + php programmers for 2 to 3 months ongoing projects based in Goa India We provide office + housing + computers etc.. A team of 3 to 5 programmers to design several websites, webshops, calculators
I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --
...already have this you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the
We need amibroker AFL language programmer on an urgent basis for one of our clients. Good payouts + bonus, But before award, you must have to establish your credentials. New freelancers are also welcome but you have to prove your abilities.
Hello, I am keen to test an idea of pulling in data from national statistics agencies that use SDMX-JSON into a website that builds charts from API. I am happy to share my chart builder with successful bidder but I simply want to see if my idea will work.
I am searching for many programmers to fix a lot of small, low cost, tasks. The task will be about Linux (Mainly Ubuntu) low level easy tasks. Example: Control Wifi Adapter in promiscuous mode to connect to a Drone, get video from a camera using Video4Linux, get audio from ALSA library... The project is on a long time range so I am posting now, and
To stimulate a project-based evaluation approach using VHDL and write a report. More information is contained in the file. Projects need to be written in VHDL and run a simulation for the program using a board. I will need the VHDL code and simulation for the timing diagram.
I created this project and fini...created this project and finished the entire code ,but for some reason it is not giving me the correct outputs.I would like help to fix the issue by editing my code. using VHDL in vivado I was able to create successful circular cordic. but when I made my AXI full and run it in SDK, it did not give me the right answer
...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the
I'm trying to build and app that will change the internet forever. For more details please contact me (Removed by Freelancer.com Admin)
I am looking for someone to create an aesthetically pleasing entity relationship diagram. There are 3 classes, one is the child of another and the child implements an interface that is nested inside of another class. I would like the diagram to have a drop shadow and other effects to make it stand out. I do not expect to pay more than $30USD as the work shouldn't take longer than 30 minutes...
...ability to extract and critically evaluate data for an unfamiliar digital design problem. The application of appropriate design methods to the VHDL design. The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors. Ability to implement your design solution on a commercially available digital Computer Aided
I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage
Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.
I need to develop a protocol in Solidity for a permissioned exchange of ERC 20 tokens to be issued as a digital representation of a real world asset. If cannot program smart contracts please don’t bid on this project. You will also need to demonstrate your solidity skills.
It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [login to view URL]
I am looking for strictly hardcore very core programmers only with Huge core experience that will be able to complete my vast programming market place web in 3 days I want experienced and serious programmers [Removed by Freelancer.com Admin]
...- language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel image to on-chip memory (M9k blocks) 2) read image from on-chip memory (using Altera/Intel's RAM-1Port vhdl IP) 3) output
i have attached the document below. And i need this on 21st of october.