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    I am developing a complete FPGA-based 5G NR Low-PHY platform for an O-RAN 7.2x radio architecture. The objective is to design, implement, integrate, optimize, and validate the complete real-time digital signal-processing chain rather than isolated FPGA blocks. The scope covers O-RAN 7.2x/eCPRI fronthaul processing, IQ compression/decompression, FFT/IFFT and cyclic-prefix processing, resource and antenna mapping, 2×2 and 4×4 MIMO, precoding and digital beamforming, DUC/DDC, channelization, interpolation/decimation, digital filtering, CFR, DPD, calibration, gain/phase correction, multi-carrier processing, timing/synchronization, and high-speed ADC/DAC interfaces. The engineer will be responsible for FPGA architecture, RTL/HLS/IP implementation, block integration, clock-domain a...

    ₹95183 Average bid
    ₹95183 Avg Bid
    32 bids

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