Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

Filter

My recent searches
Filter by:
Budget
to
to
to
Skills
Languages
    Job State
    243 jobs found, pricing in INR

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    ₹20791 (Avg Bid)
    ₹20791 Avg Bid
    7 bids

    Serializer & Desrializer Implementation using ZC706 and MTX

    ₹24900 (Avg Bid)
    ₹24900 Avg Bid
    2 bids

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou...

    ₹12550 (Avg Bid)
    ₹12550 Avg Bid
    5 bids

    I need a simple MIPS code. I will send you the task. I need it in an hour.

    ₹1328 (Avg Bid)
    ₹1328 Avg Bid
    9 bids

    Hi there Please check the document

    ₹2258 / hr (Avg Bid)
    ₹2258 / hr Avg Bid
    9 bids
    FPGA Design 4 days left

    Hi there Please check the document!

    ₹1008234 (Avg Bid)
    ₹1008234 Avg Bid
    6 bids

    I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you!

    ₹15639 (Avg Bid)
    ₹15639 Avg Bid
    6 bids

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    ₹8831 (Avg Bid)
    ₹8831 Avg Bid
    17 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    ₹8229 (Avg Bid)
    ₹8229 Avg Bid
    9 bids
    200418_Verilog 2 days left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    ₹3320 - ₹5312
    Sealed
    ₹3320 - ₹5312
    4 bids
    Conceive SDR GnuRadio blocs 2 days left
    VERIFIED

    This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send...

    ₹73971 (Avg Bid)
    ₹73971 Avg Bid
    5 bids

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    ₹1996 (Avg Bid)
    ₹1996 Avg Bid
    10 bids

    I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co...

    ₹9832 (Avg Bid)
    ₹9832 Avg Bid
    1 bids

    I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

    ₹1328 (Avg Bid)
    ₹1328 Avg Bid
    15 bids

    I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i...

    ₹18858 (Avg Bid)
    ₹18858 Avg Bid
    4 bids

    translate c++ code in systemc and implement constrained random verification methodology.

    ₹1793 (Avg Bid)
    ₹1793 Avg Bid
    4 bids

    translate c++ code in systemc. and implement constrained random varification methodology.

    ₹2855 (Avg Bid)
    ₹2855 Avg Bid
    2 bids

    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

    ₹11819 (Avg Bid)
    ₹11819 Avg Bid
    8 bids

    translate a C++ code in systemc module.

    ₹2058 (Avg Bid)
    ₹2058 Avg Bid
    3 bids

    you have to translate C++ code in systemc language.

    ₹2191 (Avg Bid)
    ₹2191 Avg Bid
    3 bids