# Verilog / VHDL Jobs

Build a calculator that can add and subtract decimals of up to 5 decimal digits. The calculator should have a display of 6 decimal digits. There should a number pad with digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and three possible operations, + (addition), - (subtraction), = (equals). The flow of the operations should be as follow: While typing the number it should be displayed right aligned, extendin...

this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comp...

MRAS SYSTEM SIMULATION USING SIMULINK NEEDED You will have 7 days to complete the work defined in scope. Your bid will not be negotiated so please read well before you bid. Payment will be 50/50 after simulation and after writting. Maximum Budget is 250USD

Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

The project has a few basic functions. 1. maintain a specific temperature 2. fire a signal to a solenoid valve in particular (adjustable) intervals. other basic functions like on off etc

Verilog simulation of two action-reaction processes

Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...