Anybody who has good experience of Verilog and it would be better if he had been using Xilinx ISE and iSim/ModelSim
Design a working prototype of the incremental backpropagation for DNN density networks in Matlab. The prototype development should include data structures for the input-to-hidden and hidden-to-output connections, and loops for the forward and backward pass.
Development to be performed on Vivado 2019.1 version using Xilinx Zynq 7020 in order to: - Acquire Galileo and GPS signals in real time (FFT and IFTT) - Track Galileo and GPS signals in real time (DLL and PLL) - Demodulation of the Galileo and GPS signals (bit synchronisation and demodulation) Timeline:30 days
This project is based on design and implementation of FMCW automotive radar system on Matlab Simulink and calculation of different parameter like speed ,distance and angle and converting signal processing block of radar system into HDL code and verifying the same scenario with same input. Later, optimization of generated HDL code and implementing HDL code into FPGA and verifying it with same inpu...
Design a block diagram for a smart watch using vivado.
I have a circuit, that in which I am using a relay to switch resistance if anyone could explain to me the way another possibility with the circuit, without any microcontroller to switch resistance with low cost and size, I want to switch 1.2ohm resistance to the existing circuit.
The project is based on designing of automotive radar system using Matlab Simulink block and to perform speed, distance, angle of azimuth and angle of elevation estimation and then performing high level synthesis to generate RTL code of design using Matlab HDL coder tool. Optimization of different parameters like speed and distance using HLS directives of generated HDL code . Implementation and ve...
Three 32-bit registers RT, RS, RD, 16-bitIMM16, 32-bit Memory Address Register(MAR), 32-Bit Memory Data Register (MDR), design arithmetic logic unit comprised of ADD/SUB and Bitwise operations.