Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    20 jobs found, pricing in INR

    Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC). 1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible. 2. Read bus should read the address to be transferred. 3. The write bus should transfer the PSS signal or the chip select...

    ₹15951 (Avg Bid)
    ₹15951 Avg Bid
    9 bids

    Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC). 1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible. 2. Read bus should read the address to be transferred. 3. The write bus should transfer the PSS signal or the chip select...

    ₹732 - ₹2195
    ₹732 - ₹2195
    0 bids

    I need you to debug a module in vhdl for me. I would like this to be developed quickly

    ₹3219 (Avg Bid)
    ₹3219 Avg Bid
    4 bids
    AVR project 6 days left

    the project is a small task to be done on AVR i will share more details in the chat. Expert only

    ₹2415 (Avg Bid)
    ₹2415 Avg Bid
    10 bids
    ₹563 - ₹4505
    7 bids
    QUARTUS II Expert Needed -- 2 5 days left
    VERIFIED

    I have a few mini projects to be done using Quartus II IDE. Experts place bid on the project and I will share more details in chat.

    ₹5927 (Avg Bid)
    ₹5927 Avg Bid
    7 bids
    Equalization in Simulink 5 days left
    VERIFIED

    Create an equalization in Simulink using given wxamples.

    ₹15249 (Avg Bid)
    ₹15249 Avg Bid
    13 bids

    Communication using PPM modulation scheme using MSP430

    ₹600 - ₹1499
    ₹600 - ₹1499
    0 bids
    Need help in DSP project 4 days left
    VERIFIED

    I need help in DSP(Digital signal processing) project

    ₹2122 (Avg Bid)
    ₹2122 Avg Bid
    18 bids

    I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.

    ₹37609 (Avg Bid)
    ₹37609 Avg Bid
    6 bids
    VHDL Expert needed -- 4 3 days left
    VERIFIED

    communication between two usarts

    ₹8122 (Avg Bid)
    ₹8122 Avg Bid
    2 bids

    I need vhdl code for uart to be implemented on basys 3 my budget is 150 usd max

    ₹8195 (Avg Bid)
    ₹8195 Avg Bid
    15 bids

    I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.

    ₹3732 (Avg Bid)
    ₹3732 Avg Bid
    4 bids
    VHDL Expert needed 1 day left
    VERIFIED

    I need to write VHDL code for LVDS transmission between two FPGAs. Please ping me if you are familiar with this.

    ₹2195 (Avg Bid)
    ₹2195 Avg Bid
    3 bids

    need VHDL code expert .........

    ₹1537 (Avg Bid)
    ₹1537 Avg Bid
    7 bids

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    ₹12366 (Avg Bid)
    ₹12366 Avg Bid
    4 bids
    Xilinx FPGA Projct 18 hours left
    VERIFIED

    The Project is to develop Verilog code to control DDR4 DRAMs via a Memory Controller and I2C interface using a Xilinx Zync+ UltraScale FPGA.

    ₹731689 (Avg Bid)
    ₹731689 Avg Bid
    1 bids

    Looking for VLSI experts having strong digital electronics and verilog concepts

    ₹5927 (Avg Bid)
    ₹5927 Avg Bid
    9 bids

    Looking for vlsi frontend experts with strong basics in digital electronics

    ₹1050 (Avg Bid)
    ₹1050 Avg Bid
    5 bids

    Risolvere un esercizio di VHDL semplice in cui si utilizza sensori, timer e altri circuiti standard. Per maggiori informazioni contattatemi in messaggio privato. Massima serietà, molto importante la professionalità e conoscere bene il linguaggio di programmazione.

    ₹2634 (Avg Bid)
    ₹2634 Avg Bid
    1 bids