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cardinal processor - open to bidding

$250-750 USD

Closed
Posted almost 9 years ago

$250-750 USD

Paid on delivery
must design a verilog code to design a cardianl processor and create test bench as per specifications
Project ID: 7391211

About the project

5 proposals
Remote project
Active 9 yrs ago

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5 freelancers are bidding on average $728 USD for this job
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I like to see the zero level functional architecture of the processor to commit this bid. I have experience in VLSI Architect for 14 years and embedded system designer for two decades. I have worked as VLS architect for companies as PortalPlayer and nComputing among others. Thanks Adi CTO Fornax Research
$777 USD in 20 days
5.0 (3 reviews)
3.0
3.0
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Hi, I had done MS in Digital Signal Processing and Digital Desing. Also I had around 8 years of industrial experience in the field of FPGAs and Verilog HDL/VHDL Coding. I had worked on several projects related to Verilog HDL. you can contact me with confidence.
$555 USD in 10 days
0.0 (0 reviews)
0.0
0.0
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we are a team of engineers having experience in related project so hope u will find our service satisfactory
$555 USD in 10 days
0.0 (0 reviews)
0.0
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I've got 30+ years of experience in RTL design & verification. Your project description isn't completely clear, but I've already implemented other micro-controllers from scratch.
$1,200 USD in 15 days
0.0 (0 reviews)
0.0
0.0
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A proposal has not yet been provided
$555 USD in 10 days
0.0 (0 reviews)
0.0
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About the client

Flag of UNITED STATES
los angeles, United States
5.0
1
Payment method verified
Member since Feb 14, 2015

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