Hi,
-FPGA design engineer since last 7 years
-Expertise in verilog/VHDL
Please find below details of the projects
TSMAC Hardware acceleration(3months)
The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction.
CSI-2 transmitter and receiver(6months)
The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards
eMMC Host Controller and Device controller(3months)
The project is to develop eMMC host and Device controller IP according to the JEDEC standards.
Mobile camera–testing(3months)
The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies
High resolution camera(6.5months)
The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor
-Test project for DDR2 accesses
-Development of calibration module
-Development of chain control module
-Development of control signal generator
-Development of Generic LUT module
-Development of Divider radix-2 algorithm
-Development of atan calculator
-Development of MCB reader state machine
Color Pipeline(15months)
The project is to develop 2D and 3D image processing algorithms on Aptina sensor
-Development of Generic Frame Buffer pCore
-Development of data compression and data packing pCore
-Development of data packing pCore
Video Processing Unit(13 months)
-Improvement in algorithms to reduce FPGA resource utilization and decrease latency
Hello,
My name is Mohamed. I have 5 years experience in Digital Design and HDL.
I checked your project description about implementing verilog code for error detection for CRC. I can guarantee to deliver high quality work. I am so familiar with it. Contact me for more details.
Regards
Hi, I have 7+ years experience working in Hardware/Embedded System design field. I'm expert in Verilog/VHDL and familiar with Xilinx/Altera FPGAs as well as their tools. I can surely help you.
Do you want to make a module for checking CRC error? Do you have idea about its input/output as well as how it connect to other modules in your system?
I am AbdulRahman, I have more than five years experience in RTL implementation using Verilog/VHDL.
I have implemented CRC code before and I have good experience with communication modules.