System Verilog- NOC design (8 bit split bus)

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Hello! Please check my reviews to know a bit about me! Thank you

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS More

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 10 years experience in digital design and well acquainted with ISE 14.5, NCverilog, Vivado 2013.4, Altera Quartus More

What exactly do you require ? A verification environment ? Will you provide the design ? Or do you also want the design ?

Over 2.5 years of experience in Verilog RTL Design, Microcontroller Projects and Algorithm Design in MATLAB in Industry and Academia. My past projects include: - PHY Layer Design on FPGA for Software Defined Radio P More

I have module IP for CRC calculation. i think it easy with me...please contact me to get draft version about CRC. Thanks Vu

Hello, I can do this project. I am expert in FPGA, VHDL, Verilog. I have done no of project on this technology. Please open your chat box for more discussion. I have 4 year experience in this field. I can do your pro More