Hi, I may be new to freelancer but I have done a few projects using Verilog hdl.
Ide : Xilinx
The verilog code (abstract) for your project is the following code, please select me if you are interested.
The outline of the program will be:
/**************
Top design module.
Name: 4 bit adder.
Ports : A, B(4 bits each), C_in, Sum, Carry.
*************/
module fourBitAdder (A, B, C_in, Sum, Carry);
input (4:0) A,B;
input C_in;
output (4:0) Sum;
output Carry;
wire c1, c2, c3;
//internals of the module
endmodule
/**************
Name: Full adder.
Ports : A, B, C_in, Sum, Carry.
*************/
module fullAdder (A, B, C_in, Sum, Carry);
input A,B;
input C_in;
output Sum;
output Carry;
//internals of the module
endmodule
/**************
Name: Half adder.
Ports : A, B, Sum, Carry.
*************/
module fourBitAdder (A, B,Sum, Carry);
input A,B;
output Sum;
output Carry;
reg Sum, Carry;
xor (Sum, A, B); //Verilog primitive
and (Carry, A, B);
//internals of the module written just to
//get your confidence on me.
endmodule
stimulus block will be defined if necessary or else the design can be stimulated graphically using Xilinx ide
Timeline :
Day 1: Start to end with any corrections.