Digital Design

Hello, I checked your project description about implementing a full adder using different techniques beside designing 4-bit adder. I can handle the task and deliver it in 6 hours Relevant Skills and Experience 5 years experience as digital design Engineer Proposed Milestones $25 USD - Final milestone Contact me for more details

Hi I can do your project as per your description

A proposal has not yet been provided

A proposal has not yet been provided

Hello, I am an electronics engineer having experience in digital system design using vhdl for more than 5 years. Relevant Skills and Experience VHDL Proposed Milestones $23 USD - VHDL Coding

A proposal has not yet been provided

A proposal has not yet been provided

Hi, I may be new to freelancer but I have done a few projects using Verilog hdl. Ide : Xilinx The verilog code (abstract) for your project is the following code, please select me if you are interested. The outline of the program will be: /************** Top design module. Name: 4 bit adder. Ports : A, B(4 bits each), C_in, Sum, Carry. *************/ module fourBitAdder (A, B, C_in, Sum, Carry); input (4:0) A,B; input C_in; output (4:0) Sum; output Carry; wire c1, c2, c3; //internals of the module endmodule /************** Name: Full adder. Ports : A, B, C_in, Sum, Carry. *************/ module fullAdder (A, B, C_in, Sum, Carry); input A,B; input C_in; output Sum; output Carry; //internals of the module endmodule /************** Name: Half adder. Ports : A, B, Sum, Carry. *************/ module fourBitAdder (A, B,Sum, Carry); input A,B; output Sum; output Carry; reg Sum, Carry; xor (Sum, A, B); //Verilog primitive and (Carry, A, B); //internals of the module written just to //get your confidence on me. endmodule stimulus block will be defined if necessary or else the design can be stimulated graphically using Xilinx ide Timeline : Day 1: Start to end with any corrections.

I have already done a project like that. It will take me like a few hours to implement it in Verilog. I provide a code with comments accompanied with proper test benches. Relevant Skills and Experience I've already implemented the specific project quite a few times as a part of something bigger for other projects. I have been taught in a previous semester Verilog and VHDL as a part of my studies. Proposed Milestones $35 USD - The whole code with test benches and everything. Additional Services Offered $45 USD - Block diagrams for each module and the final one