Please refer the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.
13 freelancers are bidding on average $43 for this job
I have 10 years of experiences in design and verifying using Verilog/SystemVerilog HDL. I am using vivado on a xilinx board Virtex7, please choose me. Best Regards
I have done computer engineering. I have studied a course Digital System Design which was all about fpga. I have done this project during this course. I did it in Xilinx Spartan 6. Hope to hear from you.
IF you like, we can start the Coding today and will complete it by today. having experienced with aorund 10 years of experience in VLSI design. Currently working in Qualcomm
I have done Mtech in VLSI design and my thesis was on FPGA implementation of binary integer decimal based floating point multiplier using verilog. So I can do your project easily. please give me one chance