Using the Logisim simulator
Designing and testing a RISC 32-bit processor
Instruction Set Architecture
In this project, you will design a simple 32-bit RISC processor with sixteen 32-bit general purpose registers: R0 through R15. R0 is hardwired to zero and cannot be written, so we are left with fifteen registers. There is also one special-purpose 24-bit program counter (PC) register that can address at most 2 42
instructions. All instructions are 32 bits. There are three instruction formats, R-type, I-type, and J-type as shown below:
8-bit opcode (Op), 4-bit destination register Rd, and two 4-bit source registers Ra and Rb.
8-bit opcode (Op), 4-bit destination register Rd, 4-bit source register Ra, and 16-bit immediate:
8-bit opcode (Op), two 4-bit source registers Ra and Rb, and 12-bit immediate
J-type format :
8-bit opcode (op) and 24-bit immediate constant
R-type instructions, Ra and Rb are two source register numbers, and Rd is the destination register number. For I-type instructions, Ra is the source register number and Rd is the destination register number. The immediate constant is 16 bits as in the MIPS architecture.
For the branch format, Ra and Rb are two source register numbers. The 12-bit immediate specifies the branch target offset. For J-type, the24-bit immediate constant is used for J (jump) and JAL (jump-and-link) instructions. It is used to update the PC register.
Eight R-type ALU instructions, eleven I-type ALU instructions, one load, one store, two branch ,one jump register, and two J-type instructions are defined. These instructions, their meaning, and their encoding are shown in the following table
The shift and rotate instructions use the lower 5 bits of Immediate constant as the shift/rotate amount. The Load Upper Immediate (LUI) shifts the immediate constant left by 16 bits to load it into the upper 16 bits of register Rd. LUI can be combined with ORI to load any 32-bit constant into a register. The 16-bit immediate constant is zero-extended for ANDI, ORI, and XORI instructions, and sign-extended for all other I-type instructions. All other opcodes are undefined and should be treated as NOPs (no-operation)
Your processor will have separate instruction and data memories with 224
Words each. Each word is 32 bits or 4 bytes. Memory is word addressable. Only words (not bytes) can be read and written to memory, and each address is a word address. This will simplify the implementation.
The PC contains a word address (not a byte address). Therefore, it is sufficient to increment the PC by 1 (rather than 4) to point to the next instruction in memory. Also, the Load and Store instructions can only load and store words. There is no instruction to load or store a byte in memory.
Implement a Register file containing fifteen 32-bitregisters R1 to R15 with two read ports and one write port. R0 is hardwired to zero.
Arithmetic and Logical Unit (ALU)
Implement a 32-bit ALU to perform all the required operations:
ADD, SUB, SLT, SLTU, OR, AND, XOR, NOR, SLL, SRL, SRA, ROR
PC-relative addressing mode is used for branch instructions.
o For branching (BEQ, BNE), the branch target address is computed as follows:
PC = PC + sign-extend (Imm12). Add the contents of PC to the sign-extended 12-bit Immediate.
Direct addressing mode is used for jumps (J and JAL): PC = immediate24.
o The JR (Jump Register) instruction copies the lower24-bit of register (Ra) into the PC register.
The LW and SW instructions use base-displacement addressing mode. The value of register (Ra) is added to the sign-extended 12-bit immediate to compute the effective memory address. Only the lower 24 bits of the address is used to address the data memory. The LW instruction loads data into register Rd. The SW instruction stores the value of register Rb in memory
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hello how are you? i have enough experience about this field Relevant Skills and Experience Circuit Design, Electrical Engineering, Electronics, Engineering, Verilog / VHDL Proposed Milestones $222 USD - 1