FPGA & ESP32 Hardware Enhancement

I’m refining a set of custom boards that combine an FPGA-based signal generator with several ESP32 modules. The immediate gap is in analog and digital circuit design: I need a fresh set of eyes to review, debug, and improve the front-end and conditioning stages so our multi-channel waveforms stay clean from kHz up into the low-MHz range. You will also find yourself touching the programmable logic; I use both VHDL and Verilog, so fluency in either (or ideally both) is welcome when tweaks to the signal-generation core are required. On the microcontroller side each ESP32 handles data processing, manages communication protocols, and drives attached peripherals, all written in C/C++. Expect to dive into that firmware whenever hardware changes ripple upward. Key objectives • Analyse and correct existing schematics and PCB layouts, paying particular attention to filtering, amplification, and noise mitigation. • Validate high-frequency paths with proper impedance control and minimise crosstalk in multiplexed outputs. • Update or create HDL modules when signal-flow or timing adjustments are necessary. • Adapt ESP32 code to align with any hardware revisions and maintain seamless data handling, comms, and peripheral control. • Document changes clearly so the team can reproduce your results and carry the design forward. Deliverables (acceptance criteria) 1. Revised schematic and PCB files that pass DRC/ERC and demonstrate measurable noise reduction on every channel. 2. HDL source that synthesises without timing violations and meets the specified frequency accuracy. 3. Updated ESP32 firmware with successful integration tests covering data processing, communications, and peripheral control. 4. A brief report outlining the modifications, test methodology, and performance metrics. If this mix of circuit craftsmanship, FPGA logic, and embedded C feels like your playground, let’s talk details and schedule.

Project ID: 40364805