4 port router synthesis in terms of area, power and performance

"Design and Verification of Four Port Router for Network on Chip" - IEEE paper implementation has to be extended.

The code needs to be modified to make certain changes for making the synthesis in terms of power and area.

Expecting these modifications along with a detailed explanation , synthesis report.

The milestones would be released in certain stages as the work is proceeded forward.

Expecting the work to be done by 15th of May,2017.

Skills: Verilog / VHDL

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Project ID: #13645430