Cancelled

4 port router synthesis in terms of area, power and performance

"Design and Verification of Four Port Router for Network on Chip" - IEEE paper implementation has to be extended.

The code needs to be modified to make certain changes for making the synthesis in terms of power and area.

Expecting these modifications along with a detailed explanation , synthesis report.

The milestones would be released in certain stages as the work is proceeded forward.

Expecting the work to be done by 15th of May,2017.

Skills: Verilog / VHDL

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About the Employer:
( 2 reviews ) denton, United States

Project ID: #13645430

5 freelancers are bidding on average $282 for this job

raulbehl

Hello! Please check my profile/reviews to know a bit about me. It would be great if I could help you out. Thank you!

$611 USD in 30 days
(42 Reviews)
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RushService

Lets discuss the further more details of .But i am not new in this field.I just want to know more details about this project to make it complete.I not only complete project but provide also full support to understand More

$200 USD in 3 days
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ccaplan

Hello, my name is Cairo. I am am Electronics Engineer with several years of experience on embedded system design and FPGA projects. Currently I am doing a PhD on Physical Instrumentation, but I am interested on Netwo More

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roshanmj

Hi Sir, I have gone through the description and the paper which you mentioned, and i found that it can be done with certain effort. and i thing you need only the designing part with verilog. not the SVC OVM part. More

$211 USD in 30 days
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Fpgabootcamp

I'll do this for a small fee, maybe free if it's simple enough, otherwise $100 if it's a few days work. free! (Although min bid accepted is 4.5$). Why? It's my first time on freelancer and need to build up a project More

$111 USD in 3 days
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