design an Sdram ddr using verilog and test, verify it using Synopsis and TETRAMAX ATPG. finally verify the same design in FPGA.
4 freelancers are bidding on average $333 for this job
I have 10 years of experiences in design and verifying using Verilog/SystemVerilog HDL. I need to improve my freelancer account, so that please choose me. Best Regards