Simple Vivado project demonstrating the use of AXI DMA. The project must include a Vivado workflow with custom editable VHDL code that will use an AXI master to read/write directly to DDR ram from PL. In addition the PS must be able to read what is written from PL using the same shared DDR RAM.
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Dear sir I have more than 9 years experience in digital design and I am a professional vivado designer in addition I already have Zedboard please check my profile also please message me so that we can discuss
Hello There, I am a professional working in the same field. I use Vivado 2014.1. I can take care of your task. Please let me know what will be source of data or you want to write some dummy data? Thanks, Gopi