RTL ASIC

$30-250 USD

Closed

Posted

over 7 years ago

$30-250 USD

Paid on delivery

I am looking for the following digital block to be synthesized. An expandable memory, where I can simply edit the number of bits I would like to write to my chip. E.g. A synchronous serial to parallel converter that I can define the number of bits depending on the application. The memory will have a data, clock, chip enable, clear line.

PLC & SCADA

Project ID: 11732977

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3 proposals

Remote project

Active 7 yrs ago

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3 freelancers are bidding on average $483 USD for this job

@loi09dt1

Please visit my profile to see my expertise. Thanks

$545 USD in 5 days

5.0

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1.4

@aghayth

Hi I guess you should define the maximum memory of your vhdl/verilog code. I mean at synthesize time. and can define a configuration register which hold the size of the memory. this register shall be written before using the memory. we have many options here depending on your application. if you have on chip SoC processor or not.

$155 USD in 15 days