Altera DE-1 SoC

Closed Posted 7 years ago Paid on delivery
Closed Paid on delivery

Fixing an existing Data Transfer Project.

Verilog / VHDL

Project ID: #13233870

About the project

6 proposals Remote project Active 7 years ago

6 freelancers are bidding on average $207 for this job

ahmedmohamed85

Dear sir I have more than 9 years experience in digital design using FPGA also I already have the Altera DE1 SOC board, please message me so that we can discuss

$222 USD in 3 days
(270 Reviews)
7.5
loi09dt1

A proposal has not yet been provided

$90 USD in 3 days
(83 Reviews)
6.2
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a More

$250 USD in 3 days
(46 Reviews)
5.4
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS More

$250 USD in 3 days
(5 Reviews)
4.6
OlektraGroup

dear Sir i can do this project. I can assure you that if you work with me once, you will always work with me for these kind of projects.

$155 USD in 3 days
(5 Reviews)
2.6