Complete Some task in Digital System Design using Vivado Software and Digilent Nexys4 DDR

Complete Some task in Digital System Design using Xilinx Vivado Software and Digilent Nexys4 DDR, Task to completed. - Finite-State Machine and Low Power Design - Greatest Common Divisor - LFSR - Creeping Line I will need a screenshot for the following task (Timing diagram and Logic gate design) and a screenshot of past work. N.B: Don't give me a price and later change it. It will not be accepted.