Memory Unit (RAM, cache)

Completed Posted 5 years ago Paid on delivery

$10-60 USD

Paid on delivery

Completed Paid on delivery

the project is based on two codes the RAM and the cache, i did the RAM design and i need the cache. the specifications that i need are available in the given word file

Verilog / VHDL

Project ID: #18185008

About the project

2 proposals Remote project Active 5 years ago

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ahmedmohamed85's Profile Picture
ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss

$60 USD in 1 day
(356 Reviews)
7.7

2 freelancers are bidding on average $50 for this job

engineeringexp's Profile Picture
engineeringexp

A Data Scientist with experience in Python, R programming, R Shiny, R studio and anything related to data science and python Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resou More

$40 USD in 10 days
(1 Review)
1.4
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