I need a Verilog/VHDL engineer

I will be implementing this on Vivado 2019 using a zynq xc7z020-1clg400c chip. 1. Create a Parameterized Counter Design a parameterized binary counter module that counts from zero to a value given as a parameter, and then resets to zero. Include a count enable input cen that enables counting only when asserted. In the example module definition below, a second parameter WIDTH is defined because the designer may want the counter to include more bits than are needed to count to MAX_COUNT. When instantiating the module you must set WIDTH to at least the integer ceiling of log2(max_count+1). Instantiate two counters as shown in the wrapper module: (code given in the images) Write a testbench to verify that your parameterized counters behave as desired. You will need to simulate the clock and reset inputs to the wrapper module. When each counter reaches its final count value, the respective A and B outputs should be asserted. Counter B should only count up when counter A ‘overflows’ (goes from its max value to zero). 2. Use the clocking wizard IP Modify the design in part 1 to use an IP module produced by the “clock wizard” to supply the two counters with a 7 MHz clock (from an input 100 MHz clock). Simulate your updated design and verify that the counters now count at the correct rate. For the timescale of the simulation to match up, make sure your simulated clock has a 100MHz frequency (10 ns period, 5ns per half-cycle). 3. Use the Integrated Logic Analyzer Modify your design so the a_val and b_val wires are internal to the module (only the A and B signals are used as module outputs). Implement the design on your board, assigning output A to LED0 and B to LED1. Assign a single switch input to enable/disable both LEDs. When you program your board, you should see LED0 stuck on while LED1 is toggling rapidly. Set up the ILA to probe nets a_val, b_val, A, and B, and define triggers to verify the circuit is operating properly when the LEDs are both enabled and disabled. 4. Create A VGA Sync Generator Use your parameterized counter module to create a VGA-sync generator. The circuit should use a 25MHz pixel clock input to generate horizontal and vertical sync signals for a resolution of 640x480 (refer to the background material for details on VGA timing). The module should have two inputs (clock and reset) and three outputs (hsync, vsync, and video_active). Video active should be asserted whenever the counters are in the active display area range. You can add optional outputs to indicate the x and y coordinates of the current pixel (this will be helpful in later requirements). Connect the VGA timing signals from the sync generator to the Real Digital HDMI IP (this will convert the VGA sync signals into the signals that HDMI and DVI monitors use). The HDMI IP requires the VGA pixel clock as well as a “5x” pixel clock. You can generate the pixel clock and 5x clock using the clock wizard IP. Drive the red ®, green (G), and blue (B) inputs of the HDMI IP with all 1’s to show a blank white screen on your display. 5. Display a Crosshair In the 640x480 screen area, draw one vertical and one horizontal line that meet in the center of the screen to form a cross-hair pattern. You will need to use the color inputs to the HDMI IP to do this. Each pixel is driven according to the values on the R, G and B inputs at the time the pixel is addressed by the horizontal and vertical counters, so you need to assert R, G, and/or B at just the right times to cause the crosshair pattern to be displayed. Note that if you are using a white background (that is, R, G, and B are always asserted), you will need to de-assert at least one of them to create a different color for the crosshair (for this requirement, your crosshair only needs to be a different color than the background). 6. Display a box on the screen Render a static square on the screen with a dimension of 32 x 32 pixels. Set the location of the box through use of module parameters.