Recursive karatsuba multiplier (16bit)

Completed Posted 6 years ago Paid on delivery

₹1500-12500 INR

Paid on delivery

Completed Paid on delivery

I need a verilog code for recursive karatsuba multiplier for 16bit signed integers.

Digital Design Verilog / VHDL

Project ID: #16210126

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5 proposals Remote project Active 6 years ago

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mastor31's Profile Picture
mastor31

Hi, I am good in VHDL and Verilog. I implemented ip core of floating multiplication, FIR filter in HDL. I am extensive experience in ISE, Vivado of Xilinx and Quartus of Altera. Please elaborate your requirement to p More

₹4000 INR in 3 days
(17 Reviews)
5.0

5 freelancers are bidding on average ₹12466 for this job

ahmedmohamed85's Profile Picture
ahmedmohamed85

A proposal has not yet been provided

₹13888 INR in 1 day
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8.1
SANGITAR's Profile Picture
SANGITAR

I have proficiency with VHDL and Verilog. I am good with Xilinx and Altera FPGA. Are you referring any IEEE paper

₹16666 INR in 30 days
(3 Reviews)
4.1
yemelitc's Profile Picture
yemelitc

Hello, This is a rather tricky project, so I raised the reward. Any particular reason for that algorithm on just a 16bit signed integer? But anyway as a Verilog HDL programmer and one who knows the algorithm, I can More

₹20000 INR in 2 days
(2 Reviews)
2.0
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