Verilog Project for school

$30-250 USD

Completed

Posted

over 10 years ago

$30-250 USD

Paid on delivery

The project report must include: 1)Project definition and characterization 2)Concept development and logical design 3)Design entry using Verilog HDL and functional simulation with enough input data and verification 4)Synthesis and implementation with the .ucf file specified 5)Time simulation with enough input data 6)Downloading and Testing Design/Synthesis/Implementation MUST be done using Xilinx ISE Tools and Spartan 3E or Spartan 6(NEXYX 3) Board. I need a freelancer that can do this project and then either walk me through the process or make a video walk through. The attached file contains the project description.

Verilog / VHDL

Project ID: 5145782

About the project

9 proposals

Remote project

Active 10 yrs ago

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Awarded to:

@amibio

Hi, I'm a Verilog HDL and VHDL expert with 15+ and 13+ years experience, respectively. I have implemented more than 125 designs for third parties/clients including MSF/DCF77 decoder, FFT, RISC processors, ASIPs for image/video processing, FSMs/FSMDs for various control and data computation tasks. I have the Pong P. Chu book at my personal library (your excerpt is from the VHDL version), and have all three of the following boards: Spartan 3, 3E and 3AN starter kits. Overall, more than 40 designs implemented and verified on these boards.

$220 USD in 4 days

5.0

(2 reviews)

3.8

@zeshannaseer

Hi dear.I can do this job..I have already worked with you I hope we can communicate better for the next [login to view URL] you want to discus please contact me.

$170 USD in 3 days

5.0

(24 reviews)

5.0

9 freelancers are bidding on average $169 USD for this job

@ahmedmohamed85

Dear sir, I am the best verilog programmer at freelancer.com, i will provide you with the project in addition to online assistance using skype

$172 USD in 3 days

4.9

(389 reviews)

7.8

@pmullappilly

Hi, I am a graduate in EEE.I have 15 years of experience in programming,electronic design and teaching.I can do this work for you. I have good experience in verilog/vhdl FPGA design. (My current project is a 32 bit RISC processor with pipe lining.) Thanks and Regards, Prasad.M

$111 USD in 7 days

5.0

(2 reviews)

2.5

@itachi23

Hi could u tell me what do u want to implement i read the document , its not assignment its like walk trought ............................................................................................................................................................................................. and i can make a video , once i know what u want exactly

$210 USD in 7 days

0.0

(0 reviews)

0.0

@Iriiine

Предложение еще не подано

$200 USD in 5 days

0.0

(0 reviews)

0.0

@jagadeesh22

I have good skills and practical knowledge to develop the requirement for the project.I have can design with easier technique which every one can understand

$77 USD in 3 days