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    89 jobs found, pricing in INR

    We need an expert of FPGA for fsm of washing machine analysis and synthesizes

    ₹6071 (Avg Bid)
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    5 bids
    Simulink to VHDL 5 days left
    VERIFIED

    I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time.

    ₹1482 (Avg Bid)
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    5 bids

    I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers.

    ₹3544 (Avg Bid)
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    7 bids

    Plz contact me. I have other code for it as well. You will just need to restructure the code and it should be good enough.

    ₹1707 (Avg Bid)
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    12 bids

    I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers.

    ₹484 - ₹3386
    ₹484 - ₹3386
    0 bids

    DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero

    ₹28313 (Avg Bid)
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    10 bids

    1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA.

    ₹50463 (Avg Bid)
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    24 bids

    need somebody good in micro controller and has ever coded using vhdl

    ₹11212 (Avg Bid)
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    18 bids

    Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB...

    ₹2900 (Avg Bid)
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    10 bids

    design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language

    ₹10117 (Avg Bid)
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    14 bids

    the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project

    ₹5348 (Avg Bid)
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    8 bids

    I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 "

    ₹11083 (Avg Bid)
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    12 bids

    Project: The project consists of multiple phases. It is to develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single...

    ₹4639 (Avg Bid)
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    I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA.

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    6 bids

    About timing violation at cross clock domain

    ₹1611 (Avg Bid)
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    1 bids

    I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks

    ₹686 / hr (Avg Bid)
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    10 bids

    i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me

    ₹644 / hr (Avg Bid)
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    10 bids

    I need someone who can do task on system verilog. Deadline is 2 days. I want someone who can start now. More details will be provided to interested freelancer

    ₹1521 (Avg Bid)
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    8 bids

    build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Accompanied with each unit s...

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    8 bids

    VHDL coding needed to be done by expert!! $30 CAD pay

    ₹1419 (Avg Bid)
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    8 bids

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