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    120 jobs found, pricing in INR

    Hello I am looking for some to build and cusotmize the opencl FPGA based on AMD etc. Especially you have rich experience with FPGA network communication.. Please send me message if you are ready with this project.

    ₹27248 (Avg Bid)
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    6 bids

    Serializer & Desrializer Implementation using ZC706 and MTX

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    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou...

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    Hi there Please check the document

    ₹2260 / hr (Avg Bid)
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    10 bids
    FPGA Design 3 days left

    Hi there Please check the document!

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    6 bids

    I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you!

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    Trophy icon Open source SDR and more 25 days left

    I would like to offer my sponsorship of a software defined radio board to student engineer or researcher to work on any open source project that will involve the community. My hardware will be the BeagleSDR add-on board as best current cape for the Beagleboard-x15. It has a FPGA, AVR microcontroller, and high speed ADC/DAC, i2c programmable clock... This open source project probably last at least ...

    ₹6646 (Avg Bid)
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    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

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    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

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    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

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    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

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    I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.

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    expert in vivado and vhdl needed asap

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    using four bit ALU, given two numbers A and B we need to find if A is divisible by B

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    I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.

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    Details later.. I will check your BASIC.. And then recruit You

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    Program a FPGA to work as a MC6803 on a device like a Digilent Cmod A7: Breadboardable Artix-7 FPGA Module. [url removed, login to view] . will need relevant information to program multiple devices.

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    Design a serial interface using Python for communication with FPGA.

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    I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture.

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