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    103 jobs found, pricing in INR

    Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly cont...

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    5 bids

    We need to develop a QPSK demodulator FPGA xilinx based.

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    We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board.

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    I'm looking for someone who can write me a verilog HDL code for a servo controller

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    7 bids

    Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details.

    ₹514508 (Avg Bid)
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    I would like someone to help me build a simple FPGA Kernel for a certain gaming system. I would like your help to improve a FPGA project we are using Altera Quartus programming software i have attached a QAR file First of all, compile it to a POF file and then send it to me and let me examine it and I will give you more instructions on how to proceed. It's not very complicated Let me ask...

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    I would like someone to help me build a simple FPGA Kernel for a certain gaming system.

    ₹9674 (Avg Bid)
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    4 bids

    I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA.

    ₹31877 (Avg Bid)
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    FPGA work .... Ended
    VERIFIED

    I would like someone to help me build a simple FPGA Kernel for a certain gaming system.

    ₹1749 (Avg Bid)
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    5 bids

    I would like someone to help me build a simple FPGA Kernel for a certain gaming system.

    ₹1322 (Avg Bid)
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    5 bids

    need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works

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    We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers

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    I am looking for a freelancer with knowledge of assembly, microcontrollers, and pcb design. The project is about creating a communication pcb for an older video game console, the Super Nintendo / Super Nes. Let's have a really basic overview of the game system : The software game code is stored within a cartdrige. When the device is powered, the game's ROM placed on the cartdrige is ...

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    Petalinux on ZC706 Ended
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    I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features.

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    Hi Constantin R., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    vhdl expert needed asap to run a code

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    I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code

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    Coding required for FPGA to SFP communication

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    Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details.

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    Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter.

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