FPGA based Area efficient DWT based watermarking alongwith cryptography

$30-250 USD

Closed

Posted

over 7 years ago

$30-250 USD

Paid on delivery

I want to implement DWT based watermarking alongwith cryptography on fpga. Requirement is it should be area efficient. Then performance is to be compared with DCT based watermarking alongwith cryptography on fpga.

Verilog / VHDL

Project ID: 11998704

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Active 7 yrs ago

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@punamsengupta

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$222 USD in 15 days

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@syedzubair786

timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:25:32 10/29/2016 // Design Name: // Module Name: mainfunc // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module mainfunc( reset ,shift,update,clk,SI,Q ); input reset ,shift,update,clk,SI; output reg [4:0]Q ; reg [3:0]count=3'b000; reg [2:0]count1=2'b00; always@(posedgeclk) begin if (reset==1) Q[3:0]=4'b0000; else begin if ((shift==1) && (SI==1)) begin count=count+1; if(count<=1) Q[3:0]=4'b0001; if(count==2) Q[3:0]=4'b0011; if (count==3) Q[3:0]=4'b0111; if(count==4) count=3'b000; end if((update==1) && (shift==1 || shift ==0)) begin count1=count+1; if(count1<=1) Q[3:0]=4'b0111; if(count1==2) Q[3:0]=4'b1010; if(count1==3) count1=4'b000; end if((shift==1)&&(update==0)) Q[3:0]=4'b0100; end end endmodule // test bench `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Cr

$66 USD in 2 days