Verilog vhdl vergleich jobs
We are seeking a VHDL FPGA programmer to develop a program for data encryption and decryption with a high level of security. The ideal candidate should have experience in VHDL programming, FPGA design, and encryption/decryption algorithms. Functionality: - The program should provide high-security data encryption/decryption that meets the client's requirements. Encryption/Decryption algorithms: - The client needs suggestions for encryption/decryption algorithms that meet their high-security requirements. The ideal candidate should have experience in suggesting and implementing secure encryption/decryption algorithms. Level of security: - The client requires a high level of security for the encryption/decryption process. The ideal candidate should have experience i...
I am looking for an experienced freelancer to work on an FPGA based project. The main goal of this project is performance optimization, and I am looking for someone with experience using the Xilinx platform, and coding in VHDL. I am looking for someone who can ensure that the project turns out as expected and meets all my requirements. Additionally, I would like the outcome of this project to have a positive impact on my organization's performance. The freelancer I choose must have in-depth and up-to-date knowledge of the FPGA architecture as well as memory control, interfaces, and system design. He/she should also possess excellent programming experience and be able to provide detailed reports and documentation in a timely manner. Moreover, I need assurance that this project...
Expand on the design of a single-cycle RV32I processor core called Archer, which implements most instructions of the RV32I base integer instruction set. Your the task will be to pipeline the processor and add hardware support for data forwarding and hazard detection.
Hello, I need code that turns on an 80% duty cycle when the feedback voltage drops below 1.5 V. I also need the voltage to be displayed on a LCD display. I need it coded in verilog to work with a DE-10 lite board.
Project for a simple security system design in System Verilog code, design and testbench.
I am looking for someone to develop a project that will allow data to be transmitted from my Field Programmable Gate Array (FPGA) to a PC. The connection type that should be used is USB and the language used to communicate must be Verilog. Data that needs to be transmitted is text only. I need a detailed solution that can handle transmission of data in a smooth, consistent manner. It should be able to identify events and their associated data while being reliable and efficient. The hardware and software involved should be thoroughly tested and debugged. The solution should also be documented and include any necessary reports/specifications. The project should be delivered in a timely fashion.
I am looking for a freelancer to design a single clock process based on RISC-V ISA using Verilog. The clock process design must have the following specific features and functionalities: The project only requires the implementation of the base RISC-V ISA, without any specific extensions. The ideal freelancer must be skilled and experienced in Verilog and have a deep understanding of RISC-V ISA. Additionally, I would prefer someone who has previously worked on similar projects and can provide examples of their work.
I am looking for a freelancer who can help me find a behavioral module that incorporates all of the methods used to implement true addition and true subtraction with a test bench module. The ideal candidate should have experience in Verilog and be able to work on a project with some design preferences. The test bench module should have a basic level of complexity.
I am looking for a freelancer to design a gas detector circuit using Verilog for the Basys 3 board. The detector should be able to sense Carbon Monoxide gas. I have a rough idea of what I want. The buzzer alarm does not have any specific requirements, but it should be loud enough to be heard. The ideal skills and experience for this job include proficiency in Verilog, knowledge of gas detection circuit design, and experience with the Basys 3 board.
I need to control the buck converter using a current mode control in digital form. That means i need to use digital PI, ADC converter, Digital PWM. For these digutal controlling parts I have to write verilog codes or have to use IP's in vivado to implement on FPGA. At the end I need to do PCB design for the buck converter and after that I have to combine them and observe the results on oscilloscope.
Hello! I am in need of a freelancer to help me with a project creating a car elevator controller. The controller will be created using Vivad Verilog code and fpga implementation. I am looking for someone who can provide a detailed project proposal in their application. It is also important they have past work and experience in the same field. I won’t need any type of remote access for this project so please do not include any advice on that as part of your proposal. If you believe you are suited for this project and would be interested in working with me, please apply and include your detailed project proposal. I look forward to hearing from you!
I am looking for help with creating a System Verilog code for a sequential multiplier and a floating point multiplier. For the multiplier, I would need both types: sequential and floating point. The verification of the functionality is required. I am necessary looking for an experienced engineer who truly understands what's needed for this requirement and can efficiently and quickly develop the code for it.
As part of a development project, I need help designing verilog code on Xilinx. I'm looking for experienced freelancers with the technical skills to properly implement the design. I need complete control when it comes to providing feedback and making sure the progress is on track. The right candidate should have a solid track record and demonstrate their expertise in the same field before applying to the job.
I have a task in VHDL looking for VHDL code to control Epson printhead.
I'm looking for a VHDL 1st-in 1st-out (FIFO) project to be completed. I need a Verilog code to complete the FIFO example. Also, syntax is very important, therefore, I am attaching an example (LIFO) to illustrate the syntax.
write a verilog code for a straight line equation y=mx+c where all m,x and c are 32 bit and even after arithmetic operations between m,x,cand y the final values should always be truncated to 32 bit(for example m*x gives a 64 bit value which has to be truncated to 32 bit after the multiplication) . The final value should be in 4.28 format [i.e.,4 for integer part and 28 for decimal part(fractional part)] . In the integer part one bit will be for sign and there are left with 3 more bits which can have a maximum value till 7, and the decimal part consists of 28 bits ,so the value will be + or - 7.9 for 4.28 m and x should take decimal values
I need to use GitLab CI to check for students' work assignment (language VHDL (run with GHDL) if that matters). The idea is that I have a "secret" testbench, which is compiled with student's code (submitted as git commit to GitLab), and the job needs to check if the submission passes the test. There must be zero possibility for the student to misuse the GitLab to get access to the secret code. Preferably the secret code is stored and run in a separate computer (than gitlab-runner). Deliverables: - Description how the objectives are met - Installation instructions (if any) - Example project with CI pipeline - Source codes of customized scripts / code (C or C++ allowed). Please note: - GitLab CI allows to run arbitrary code in the CI-job, thus the student wi...
Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs. Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.
...a project in the labs during the 9th to 13th week of the semester. The practical demonstration will take place last week. Using BUT e-learning, students submit a link to the GitHub repository, which contains the project in Vivado, the necessary images, documents and a descriptive README file. The submission deadline is the day before the demonstration. The FPGA source codes must be written in VHDL and implementable on the Nexys A7-50T board in the development tools used in the laboratory during the semester. Make testbenches for all your new components. Physical implementation on FPGA is necessary, computer simulation is not sufficient. Never, ever use rising_edge or falling_edge to test edges of non-clock signals under any circumstances! In a synchronous process, the first...
I'm looking for an expert in VHDL and Quartus II from Pakistan to design a specific digital system of intermediate complexity. The ideal freelancer will have experience in designing digital systems using VHDL and Quartus II.
BCD multiplier development using Verilog HDL for Xilinx FPGA technology Input/Output Format: - Desired input/output format is Binary Testbench: - Testbench required for the Verilog code Ideal Skills and Experience: - Proficiency in Verilog HDL - Experience in BCD multiplier development - Expertise in Xilinx FPGA technology - Familiarity with Binary input/output format - Ability to create a testbench for Verilog code Goals: - Develop a functional BCD multiplier using Verilog HDL - Ensure the Verilog code passes the testbench - Optimize the design for Xilinx FPGA technology.
Design a push-button door lock that uses a standard tele-phone keypad as input.
I need a code in VHDL for a custom IP to communicate with the DDR4 MIG, it can be through a DMA block with FIFO over the AXI bus. Everything must be done on the PL side, and must have the basic functions of writing and reading a data at a memory address. The code will be tested on the ZCU104.
This is a project where you will use a DE 10 Standard Board to detect audio data. It should detect snaps and under instructions, look at ideas in the instruction areas, there are highlighted other functions there. The files and everything else necessary to complete to complete the poject are in this google drive. Thank you.
using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C
I need a full verliog code that will output a "32-bit microprocessor using an FPGA board" 1. High level text description to describe HOW you are implementing your project. 2. DETAILED Block Diagram(s) showing design and detailed interconnections. 3. List of tasks completed 4. List of things I need to simulate, debug, and demonstrate 5. Data sheets for each IC used in your design. 6. Worst Case analysis - show tables / spread sheets in progress in process for Noise margin, Loading, Timing 7. I WILL NEED A VIDEO EXPLAINING HOW THE CODE WORKS (IN ENGLISH) 8. ALSO PICTURES OF THE CODE RUNNING SMOOTHLY NO PLAGIARISM PLEASE PLEASE COME UP WITH YOUR OWN CODE
Embedded Linux with FPGA capability. From VHDL to application level programming.
We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language
Looking for FPGA Developer who has experience in VHDL on SoC FPGA architecture
I’m looking for a talented freelancer to help me design a LIN Bus controller FPGA, in VHDL. To be considered for the job, candidates should include past work in their application and provide relevant experience related to this project. Any working code previously developed is a plus. Deadline for the delivery 20th April 2023. A quotation is required, together with the proof of previous expertise of the working code already developed It will be required to 1. deliver VHDL source code for LIN master bus controller 2. testbench with a Verification module, or any other sort of mechanism to emulate a node 3. Integration and testing of a simple test code on hardware provided by us 4. documentation
Europe, Italy timezone preferred. Lead the activity for porting FPGA design to Silicon technology (memory replacement, ...) Carry on simulations of the updated RTL design to check that the functionality remains unchanged Execute static and formal verification of...check that the functionality remains unchanged Execute static and formal verification of RTL code using appropriate tools Run trial synthesis on the RTL design and check the timing violations Lead the activities for SoC sub-block Static Timing Analysis. Required Skills (expert): VHDL language Digital ASIC design flow Use of digital simulations with standard industry simulators (Mentor QuestaCore) Static and formal RTL verification (e.g. Synopsys Spyglass) Synthesis tools (e.g. Cadence Genus) UVM and System Verilog...
Program the Basys 3 using the Cordic IP Integrator to generate: the hyperbolic sine and hyperbolic cosine of an angle parameters: You must enter the angle in degrees using the switches, so that the vhdl code includes its respective conversion to radians. This angle should be shown on the 7 segment displays. Pressing btnu the displays should then show the (hyperbolic sine) of the entered angle, and pressing btnd should show the (hyperbolic sine) of the angle.
The company is searching for external collaborators to design and test a Video test pattern generator in VHDL. The module shall be configurable for different pixel bit, num,ber of pixel per clock, different pattern generated, resolution, frame rate, colour format, video output sequence
Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?
Hi Ahmed K., I noticed your profile and would like to ask for help with debugging a verilog project. We can discuss any details over chat.
Hi Sardar Hasnain A., I noticed your profile and would like to ask for help debugging a verilog project on vivado. We can discuss any details over chat.
Turbo codes are error correction codes that are widely used in communication codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Turbo decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder Turbo encoding and decoding is done using Octave, Xilinx Vivado, Cadence system is implemented and synthe...
1)Using VHDL and the Xilinx Vivado Tools, design and implement a 4-bit ALU whose functionality is compliant with the TTL MSI 74LS381A specifications. The design must use a VHDL behavioral modeling coding style and can include concurrent and sequential statement types. Source code modules must include liberal commenting to clarify and explain function and operation your code. 2) Create a test bench VHDL module and use the Vivado Simulator to test/verify proper operation of the ALU’s functions with all input data patterns specified in the 74LS381A functional table. Recommendation: to make comparison of simulated results to those listed in the functional table easier, apply the external stimulus input patterns in the same “row” order as inputs are listed...
I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report
Image processing digital electronic system
Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.
Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
...generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board an...
I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.
...create a verilog code for image dehazing. The image is converted into a text file using Matlab(all pixel values are converted into corresponding hexadecimal values). This text file is given as the input to the verilog program. First we need to find the minimum of RGB value of each pixel and create a matrix. Then we need to consider a small window/mask in the new matrix and find the minimum of that mask and sweep the mask through the entire new matrix to create the darkchannel image. Then by using the equations using the darkchannel prior algorithm we need to recreate a haze free image. (the output of the verilog code will be a text file and is recreated into an image using Matlab. I am attaching a reference paper. I just need to get the basic dehazing part fro...
I need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.
